Improvements in Fabrication Process for Nb-Based Single Flux Quantum Circuits in Japan : Recent progress in superconductive digital electronicsHIDAKA, Mutsuo; NAGASAWA, Shuichi; HINODE, Kenji et al.IEICE transactions on electronics. 2008, Vol 91, Num 3, pp 318-324, issn 0916-8524, 7 p.Article

Characteristics of driver and receiver circuits with a passive transmission line in RSFQ circuitsSUZUKI, Hideo; NAGASAWA, Shuichi; MIYAHARA, Kazunori et al.IEEE transactions on applied superconductivity. 2000, Vol 10, Num 3, pp 1637-1641, issn 1051-8223Article

Improvement of fabrication process for 10-kA/cm² multi-layer Nb integrated circuitsSATOH, Tetsuro; HINODE, Kenji; NAGASAWA, Shuichi et al.IEEE transactions on applied superconductivity. 2007, Vol 17, Num 2, pp 169-172, issn 1051-8223, 4 p., 1Conference Paper

Research on Effective Moat Configuration for Nb Multi-Layer Device StructureFUJIWARA, Kan; NAGASAWA, Shuichi; HASHIMOTO, Yoshihito et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 603-606, issn 1051-8223, 4 p., 1Conference Paper

Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point AddersPARK, Heejoung; YAMANASHI, Yuki; NAGASAWA, Shuichi et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 634-639, issn 1051-8223, 6 p., 1Conference Paper

SFQ Propagation Properties in Passive Transmission Lines Based on a 10-Nb-Layer StructureTAKAGI, Katsumi; TANAKA, Masamitsu; IWASAKI, Shingo et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 617-620, issn 1051-8223, 4 p., 1Conference Paper

Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm² Nb ProcessKAINUMA, Toshiki; SHIMAMURA, Yasuhiro; MIYAOKA, Fumishige et al.IEEE transactions on applied superconductivity. 2011, Vol 21, Num 3, pp 827-830, issn 1051-8223, 4 p., 1Conference Paper

100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm² Nb Multi-Layer Process : Frontiers of Superconductive ElectronicsYAMANASHI, Yuki; KAINUMA, Toshiki; YOSHIKAWA, Nobuyuki et al.IEICE transactions on electronics. 2010, Vol 93, Num 4, pp 440-444, issn 0916-8524, 5 p.Article

Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active LayerSATOH, Tetsuro; HINODE, Kenji; NAGASAWA, Shuichi et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 167-170, issn 1051-8223, 4 p., 1Conference Paper

Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths ProcessorKATAEVA, Irina; AKAIKE, Hiroyuki; FUJIMAKI, Akira et al.IEEE transactions on applied superconductivity. 2011, Vol 21, Num 3, pp 809-813, issn 1051-8223, 5 p., 1Conference Paper

Measurement of Superconductive Voltage Drivers up to 25 Gb/s/chHASHIMOTO, Yoshihito; SUZUKI, Hideo; NAGASAWA, Shuichi et al.IEEE transactions on applied superconductivity. 2009, Vol 19, Num 3, pp 1022-1025, issn 1051-8223, 4 p., 1Conference Paper

Single flux quantum counting sinc filter with multistage decimation structureHASEGAWA, Haruhiro; HASHIMOTO, Tatsunori; NAGASAWA, Shuichi et al.Superconductor science & technology (Print). 2002, Vol 15, Num 1, pp 161-164, issn 0953-2048Article

Superconducting latching/SFQ hybrid RAMNAGASAWA, Shuichi; HASEGAWA, Haruhiro; HASHIMOTO, Tatsunori et al.IEEE transactions on applied superconductivity. 2001, Vol 11, Num 1, pp 533-536, issn 1051-8223, 1Conference Paper